Where to Find Eric at DesignCon 2016

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There is no other conference like DesignCon. For more than 25 years, it has been the place to be if you are involved in signal integrity or power integrity.

DesignCon technical papers are often the most cited references in the state of the art technologies used in high performance electronics products. The trade show is a who’s who of companies offering solutions to accelerate ever higher speed designs. And there is no greater collection of experts under one roof at the same time anywhere else in the world.

This year at DesignCon, my schedule is already filling up. Here are the specific events I am scheduled for. The rest of the time, I will be attending talks, walking the show floor and standing around with my cousins at the Teledyne LeCroy booth, 735. Please stop me if you see me and say hi!

Schedule for Eric Bogatin at DesignCon 2016

Tues Jan 19, 9-12 am: SI Boot camp part 1: S-parameters

Tues Jan 19, 1:30-4:30 SI Boot camp: part 2 High Speed channel Design: 

Wed, Jan 20, 1-1:15 pm, Forensic Analysis- A Who dun it mystery with audience participation, at the Teledyne LeCroy booth 735

Wed Jan 20, 2:30 – 3:10 Speed training in ChipHead Theater: “The most important design principle in power integrity” With Eric Bogatin, Teledyne LeCroy and Larry Smith, Qualcomm

Wed Jan 20, 3:45 to 5 pm: Moderating the Panel:  Optics vs. Copper for In-Chassis Connections @ 56-112Gbps: Is Copper Still a Viable Solution?

Thurs, Jan 21: 8:30 to 9:10 am, A New Characterization Technique for Glass Weave Skew Sensitivity, technical paper,

Thurs, Jan 21, 1 – 1:15 pm, “Fingerprints of Pathological Channel Models”, at the Teledyne LeCroy booth 735

Thurs Jan 21: 3:45- 5 pm Moderating the panel: Target Impedance and Rogue Waves,

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