HSDD-20-22 Routing and terminations part 3

• Using HyperLynx to simulate clocks, step response, signle bit response, PRBS and eye diagrams
• Why a clock signal is NOT a good signal to evaluate a circuit that has ISI
• An interesting puzzle to consider in your lab report and a good exercise in consistency tests
• Termination stubs
• Limitations in cluster load routing and tgree topologies
• Limitations in daisy chain and linear routing topologies
• Summary of best design practices for routing and terminations
• Summary of HyperLynx simulation labs for routing and terminations