HSDD-40-50 2017 week 15 the PDN

• The PDN are all the interconnects from the VRM to the pads on the die
• Power Integrity is not one problem, it's 12 problems
• This lecture focuses on 2: Vdd core noise and cavity noise from vias
• Via to via noise is about via to cavity noise then cavity noise to via noise
• Largest source of caavity noise is the high impedance peaks
• Reduce via to via noise by reducing cavity impedance
• The challenge in Vdd core PDN design is reduce the peak impedances
• Biggest problem to fix is the Bandini Mountain
• Make board level impedance look like a resistor to damp out Bandini Mountain
• Which is better, 1 value of capacitor or 3 values? neither are very good.